D-RAM modules are standard memory modules for main memory. D-RAM memories comprise large scale integrated transistors and capacitors. In order to maintain the information, the memory content has to be continually refreshed in this case (refresh). A synchronous D-RAM (S-DRAM) permits the memory access without additional waiting cycles. In this case, the data transfer between the S-DRAM and an external data bus is effected synchronously with the external clock signal.
FIG. 1 shows an S-DRAM memory module according to the prior art. The S-DRAM memory module is connected to an external control bus, to an external address bus and to an external data bus. Via command PADS, the control commands present on the external control bus are read in by an integrated command receiver and the reception signals are applied, after having undergone signal amplification, to a command decoder. The command decoder decodes the applied control commands, which have a width of 4 bits, for example, to form internal control commands, such as, for instance, write (WR) and read (RD). The S-DRAM comprises a state machine or a sequence controller which controls the internal sequences in a manner dependent on the decoded internal control commands. The sequence controller is clocked by a clock signal. For this purpose, an external clock signal CLKext is applied to the S-DRAM and signal-amplified by an integrated clock signal receiver. The amplified clock signal is distributed by a clock tree in a tree-like manner in the integrated S-DRAM and passes via an internal clock line to a sequence controller. The external clock signal is furthermore applied to a delay locked loop DLL. The delay locked loop DLL effects a negative phase shift of the external clock signal CLK that is present. The internal DLL clock signal leads the external clock signal in order that the data are present synchronously with the external clock signal at the data pads. The output signal driver OCD (off chip driver) of a data path, said output signal driver being integrated in the S-DRAM, is clocked with the DLL clock signal DLLCLK. Connected downstream of the delay locked loop DLL is a propagation time element which forms an internal clock signal (VE-CLK) which is simulated identically to the external clock signal, i.e. VE-CLK is completely synchronous with CLKext. The propagation time element in this respect compensates for the negative phase shift of the delay locked loop DLL.
The internal sequence controller generates control signals for the internal operating sequence of the S-DRAM in a manner dependent on the decoded commands. The sequence controller generates an RAS signal (row address strobe) for driving a row address latch and a CAS signal (column address select) for driving a column address latch. The row address latch and the column address latch are connected to an address signal receiver of the S-DRAM via an internal address bus. The S-DRAM receives an external address via the external address bus at the address PADS, the address signals present being signal-amplified by an address receiver. In order to save terminals, the address is input in two steps in DRAM memories. In a first step, the row address bits are loaded with the RAS signal into the row address latch. In a second step, the column address bits are loaded with the CAS signal into the column address latch. The address bits are applied to a row and column decoder, respectively, for access to a memory cell within the matrix-type memory cell array. The row address latch and the column address latch and also the row decoder and column decoder together form an address signal decoder. For the refresh of the memory cells, the sequence controller generates a refresh control signal. A refresh counter, which receives said refresh signal from the sequence controller, successively generates all existing row addresses, which are then applied to the address bus. The sequence controller generates an RAS control signal for this purpose. All the word lines are activated in this way. Through the activation of a word line, all the memory cells connected to it are refreshed.
The memory cell array is furthermore connected to read/write amplifiers. The number of read/write amplifiers depends on the memory architecture, the word width and the prefetch. Given prefetch 4 with a word width of 32, by way of example, 128 read/write amplifiers are in operation simultaneously. If four independent memory banks are provided, for example, a total of 512 read/write amplifiers are integrated on the memory chip.
Via the read/write amplifiers, a data bit is in each case written to an addressed memory cell or read from it. The read/write amplifiers are connected to an internal data path of the S-DRAM via an internal data bus. Via the data path, the data present in the external data bus are written to the S-DRAM synchronously and output from the S-DRAM synchronously. The data path is connected to the data PADS of the S-DRAM.
For reading in the data, the data path acquires a data receiver for receiving the data that are present externally. An internal driver circuit for the data to be written (WR driver) carries out a signal amplification of the received data and outputs the read-in data to the read/write amplifiers via the internal bus. The driver circuit WR driver is driven by a write latency generator which is clocked by the internal clock signal VE-CLK. For its part, the write latency generator is connected to a decoder.
For synchronous outputting of data, the data path contains a data FIFO register, downstream of which an output data driver circuit (OCD driver) is connected. The FIFO register is driven by the read/write amplifier by means of an input pointer and by a read latency generator by means of an output pointer or a time-delayed data enable signal. The read latency generator is likewise connected to a decoder.
The two decoders for the read latency generator and the write latency generator are connected via internal control lines to a mode register in which the data for controlling the operating modes within the S-DRAM are stored. The mode register can be initialized by a mode register set command via the internal address bus. The mode register is initialized after the switch-on. Before external control commands are applied to the S-DRAM, the mode register is initialized. The mode register contains control data for the CAS latency, for test modes and for a DLL reset.
The sequence controller generates, in a manner dependent on the external control commands, an internal write command PAW for activating the write latency generator and an internal read command PAR for activating the read latency generator.
FIG. 2 shows the FIFO register contained in the data path of the S-DRAM memory. The FIFO memory is on the one hand connected to the internal data bus of the S-DRAM and is on the other hand connected, on the output side, to the OCD driver. Via the data input lines of the internal data bus, the FIFO register receives the data to be output and outputs them via data output lines to the OCD driver connected downstream. Since the bus width of the internal data bus is higher than the bus width or word width of the external data bus by a prefetch factor PF of the S-DRAM, a parallel-serial conversion of the data is effected by the FIFO register. If the S-DRAM has a word width of 32 bits, for example, i.e. if the external data bus has 32 data bit lines, the bus width of the internal data bus given a prefetch factor of four is four times thirty-two bits, i.e. 128 data lines. The internal data bus therefore comprises four logical internal data buses each comprising a word width of 32 bits. The corresponding data bits, i.e. data bit 0 to data bit 31 of the four logical internal data buses (Load 0, Load 1, Load 2, Load 3) are respectively connected to a conventional FIFO data register, as is illustrated in FIG. 3.
FIG. 3 shows a FIFO register according to the prior art for the parallel-serial conversion of data. The FIFO register contains a plurality of shift registers SR each comprising series-connected data holding elements DHG. The number of series-connected data holding elements DHG corresponds to the number of data input lines connected in parallel. In the case of the S-DRAM memory illustrated in FIG. 1, each FIFO register element, as is illustrated in FIG. 3, has four data input lines, i.e. the width of a shift register SR is equal to the prefetch factor PF of the S-DRAM memory and has a value of four. With the rising signal edge of the output control signal OUTP and also with the falling signal edge of the output control signal OUTP, the data holding elements DHGi accept a datum from the data holding element DHGi−1 connected upstream and forward the datum to a data holding element DHGi+1 connected downstream. In this case, a data holding element DHG may comprise two flip-flops driven in antiphase or flip-flops which, on both signal edges, can simultaneously receive new data and pass on the previous data. The data holding elements DHG are driven by input control signals (Input) and by output control signals (Output). The data holding elements of the various shift registers SR are driven cyclically for reading in and outputting data.
A data input indication signal is fed to a first counter, which cyclically outputs input control signals to the shift registers SR. In the case of an S-DRAM, the data input indication signal is generated by the read/write amplifier circuit and transmitted to the FIFO register. The data input indication signal indicates to the FIFO register that the data present on the internal data bus are valid and can be accepted.
The read latency generator S-DRAM generates a data output indication signal and feeds it to two different counters within the FIFO register. One counter cyclically generates data output control signals (Output) and cyclically drives the data holding elements of the shift registers SR therewith. The data output indication signal is furthermore fed to a counter for generating enable signals (EN) for cyclically driving data signal drivers.
The FIFO register according to the prior art as illustrated in FIG. 3 has a register depth N, i.e. N storage registers SR are provided which can be loaded one after the other. The loading or filling of a shift register SR takes place by means of the associated input pointer or the associated input control signal.
Each shift register SR has a register width M, which has a value of four in the example illustrated in FIG. 3. The width M of the shift register is equal to the prefetch factor PF of the S-DRAM.
The depth N of the FIFO register is chosen in a manner dependent on the prefetch factor PF, the maximum CAS read latency and the minimum permitted interval between two read accesses. In a preferred embodiment, the depth N of the FIFO register likewise has a value of four, by way of example.
The data bits loaded into the FIFO register originate from the memory cell array and are fed to the FIFO register via the internal data bus. The four loaded data bits are driven onto the same input-output data pad of the external data bus. The read-out of the FIFO register takes place by means of a so-called output pointer (Output), each shift register SR cyclically receiving an associated output control signal from the counter.
FIG. 5 shows the signal sequences in a FIFO register for the parallel-serial conversion of data. The FIFO register is clocked with a clock signal CLK which is formed by the DLL-CLK clock signal in the case of the S-DRAM memory illustrated in FIG. 1. The four data bits (load[0:3]) that are to be read into the FIFO register are present on the data bus lines of the internal data bus. In the example illustrated in FIG. 5, the FIFO register has a depth N of four, i.e. contains four shift registers SR. The internal counter of the FIFO register generates, from the data input indication signal, four input control signals (INP0 to INP4) for the four shift registers SR. The input control signal in each case comprises an individual signal pulse.
From the data output indication signal originating from the read latency generator, the second counter generates data output control signals (Output 0 to Output 3) for the four shift registers SR, each data output control signal (Output) comprising two signal pulses with four signal edges. The number of signal edges of the data output control signal for a shift register SR corresponds to the width M of the shift register SR, i.e. likewise four signal edges in the example illustrated in FIG. 3. Furthermore, a signal generator generates an enable control signal EN for the four data signal drivers.
The FIFO register according to the prior art as illustrated in FIG. 3 has the disadvantage that undefined data intermediate states, so-called data garbage, can occur during a changeover operation from the read-out of a first shift register (SRi) to the read-out of the next shift register (SRi+1). This is due to the fact that the enable control signal for the data output drivers does not occur with absolutely accurate timing with the associated data output control signal, i.e. the enable signal is not exactly time-synchronous with the associated output pointer signal for the storage register. The undefined data states occur since the enable signal (EN) already opens the data driver stage when the incorrect data value is still being driven from the shift register. Undefined data states arise since the signal edges of the control signals are not infinitely steep or the switching operation requires a finite time.
If, as can be seen from FIG. 5, the enable control signal En0 for the data output driver of the first shift register SR0 has a rising signal edge, the associated data output driver is activated. Afterward, the shift register SR0 receives the data output control signal (OUTP0) with four signal edges, namely two rising signal edges and two falling signal edges. With each signal edge of the data output control signal (OUTP0), the data content of the last data holding element DH0 of the shift register SR0 is driven on by the data output driver. In order that the Load 3 data bit which was originally loaded into the data holding element DHG3 of the shift register SR0 is also driven onto the data output line for the entire pulse width of a pulse of the data output control signal (OUTP0), i.e. for half the cycle time of the clock signal CLK, the enable control signal En0 would have to be completely contemporaneous or synchronous with the rising signal edge of the data output control signal (OUTP1) for the next shift register SR1 and with the rising signal edge of the associated enable control signal EN1. This cannot be guaranteed, however, since the switching operation requires a finite time or the control signal edges are not infinitely steep. In the serial data output stream, therefore, an undefined data state arises in the transition region and continues via the data output driver OCD on the external data bus. This makes it considerably more difficult for a connected processor to accept the data because the width of the data eyes for the valid data becomes narrower. In particular at very high clock rates of a few hundred megahertz, the undefined data states can lead to an error in the data acceptance by the data processor.